DesignCon 2012 On-chip Jitter and system Power Integrity

On-chip Jitter induced by switching chip logic is often the reason why a device fails to achieve high operating frequency, or low bit error rate (BER). Therefore, research of on-chip Jitter is crucial for high speed design. In this paper, the method for measurement of on-chip Jitter is described. Using this method Jitter is studied in Frequency, Time, Spatial domains, and versus Decoupling. It is shown that the common approach to the reducing on-chip voltage variations and jitter by extensive decoupling on PCB leads to raising jitter instead of lowering it. It is demonstrated how Jitter peaks and PDN’ resonances might be evaluated through Jitter measurements. Using these data the system voltage variations are simulated in Time Domain for the stationary and non-stationary aggressor and victim; the Jitter behavior is evaluated base on simulations results. The paper describes practical methodology to measure on-chip jitter, evaluate PDN performance, and guide the design to achieve low noise and jitter in a system of Chip-Package-PCB-Decoupling. Author Biography Iliya Zamek is one of the pioneers in the field of Jitter. He started as an engineer and grew to system architect / project manager working on ATEs for VLSI, SRAM/DRAMs, and instrumentation in ―Quartz, Russia’s leader in measurement and instrumentation equipment. He founded and led a startup, which evolved into a successful company. For over 15 years he worked for a leading Russian measurement Instrumentation Corporation ―Quartz‖, where he developed ATEs for VLSI, SRAM/DRAMs, and instrumentation, and progressed from engineer to system architect / project manager of comprehensive design projects. He founded a startup, which resulted in a successful company. In the US, he worked for a leading manufacturer of crystal oscillators, Q-Tech Corporation, where he designed many devices with Flight and Space rate requirements. He worked as a MTS in Altera Corp. and as a consultant for different companies, including Intel Corp. For the last 9 years, he has led R&D projects for nm-devices characterization and development, including research of on-chip Jitter and Signal and Power Integrity. He is currently a principal engineer with Semtech Corp., working on high speed Transceivers and Serdes devices. He received his BS and MS in Physics and Electronics, and a PhD from Nizhniy Novgorod State University. He has published more than 50 papers, and has been granted 20 patents.